FLIP-FLOP In Digital Systems

Flip-flops are asynchronous bistable components. The term asynchronous means that the output will change state only if there is a trigger on the clock input. The internal circuit of a flip-flop consists of several logic gates, while the logic gate consists of basic components such as transistors, resistors and diodes.

In a computer system, the flip-flop functions as a memory element, which is a device that can store binary data. In general, the symbol of a flop-flop is given in Figure 1.

Figure 1   General symbol of a flip-flop 

Types of Flip-Flop

RS-Flip-Flop with NAND

  1. S = R = 1: This is a normal condition, not will affect the output or the state of the output remains as in the initial conditions.
    2. S = 0, R = 1 : this condition will always result in the output Q = 1 and will always remain even though S has returned to the High condition.
  2. S = 1, R = 0 : this condition will always result in the output Q=0 and will always remain even though R has returned to the High state.
  3. S = R = 0 : This condition is a confused condition so it should not be used in an application design.

From the description above, it is clear that S and R are low active. The internal circuit of the RS-FF is given in Figure 2, with the correct table given in Table 1.

Figure 7.2 RS-FF (NAND) Internal Circuit 

Figure 7.3 RS-FF(NAND) Symbol

Table 1    RS-FF(NAND) Truth Table

Figure 4 shows the working time diagram of RS FF(NAND), assuming the initial condition Q = 0.

Figure 4   example of the output form of RS-FF (NAND)

  1. In the initial condition, S=R=1, this condition does not change the state of Q= 0.
    2. At T1, S=1, R=0, this condition does not change the output of Q because it is already in a reset state (Q=0).
  2. At T2, S = 0, R = 1, this condition causes the Q = 1
  3. At T3, S = 0, R = 1, this condition causes the Q = 1 (remained the same at T2)5. On T4, S=1, R=0, this condition causes a change in Q=0. From the above description, it shows that the output will be maintained until there is a change in the input that is contrary to the previous input condition.

RS-Flip-Flop with NOR

A flip-flop made from a NOR gate will exhibit the opposite behavior to RS-FF(NAND) in terms of triggering transitions. The workings of this flip flop are described as follows.

  1. S = R = 0 : This is a normal condition, will not affect the output or the output state remains as in the initial conditions.
    2. S = 1, R = 0: this condition will always result in the output Q = 1 and will always remain even though S has returned to the Low condition.
  2. S = 0, R = 1: this condition will always result in the output Q = 0 and will always remain even though R has returned to the Low condition.
  3. S = R = 1: This condition is a confusing condition so it should not be used in an application.

From the description above, it can be seen that S and R are high active (High), the opposite of RS-FF(NAND) which is low active. The inner circuit of the NOR Latch is given in Figure 5, and the symbols are given in Figure 7.6, and the truth table is given in Table 2.

Figure 5    RS-FF (NOR)

Figure 6       Symbol RS-FF (NOR)

Table 2   RS-FF (NOR) Truth Table

Figure 7 shows the RS-work time diagram -FF (NOR), assuming the initial condition Q = 0.

Figure 7   example of the output form RS-FF (NOR)

  1. In the initial conditions, S=R=0. Does not change the state (Q=0). 2. At T1, S=1, R=0, this condition causes Q=1
  2. At T2, S=0, R=1, this condition causes Q=0
  3. At T3, S=0, R=1, this condition causes Q=0 (same as the previous condition)
  4. At T4, S=1, R=0, this condition causes Q=1

From the description above, it shows that the output will be maintained until the opposite input changes with the previous input conditions.

RS-Flip-Flop with Clock

This type of flip-flop, in addition to input S and R, also has a clock signal input so it is often called SR-FF with Clock. Figure 8 is a symbol for this flip-flop, with a trigger on a positive transition, meaning that the output will change only during an up transition of a given clock pulse. The correct table is given in Table 3. Inpus S and R function as discussed previously.

Figure 8  RS-FF with rising transition Clock

Table 3   Truth Table of RS-FF rising transition

 

Figure 9 Time Diagram of application examples  of RS-FF  rising transition

The timing diagram in Figure 9 is an illustration of how this flip-flop works with the following analysis.

  1. At the initial state all inputs are 0, so is the output Q=0 2. At the time of the first clock pulse up transition (point a), where S=R = 0, then this condition does not change the state so that Q remains 0.
  2. During the transition, the second clock pulse increases (point c), where S = 1 while R is still 0, this condition changes the state of Q to 1.
  3. During the transition, the third clock pulse increases (point e), where S = 0 while R =1, this condition changes the state of Q to 0.
  4. At the time of transition the fourth clock pulse rises (point g), where S=1 while R=0, this condition changes the state of Q to 1.
  5. At the time of transition the clock pulse increases the five conditions remain the same in point 5 above because the conditions S and R do not change.

From the description above, it should be noted that the down transition of the clock pulse has no effect on the output of the flip-flop. Figure 7.10 shows a down transition type SR-FF, which is indicated by a small circle on the clock terminal. The truth table is given in Table 4.

Figure 10  RS-FF with Clock types of transitions down

Table 4   Truth Table of RS-FF transition down

 

JK Flip-Flop with Clock

This type flip This flop has 3 input signals, namely clock, J, and K. Figure 11 is a JK-FF symbol for the up transition type, meaning that the output will change only when an up transition occurs from a given clock pulse.

The correct table is given in Table 7.5. The inputs J and K function to determine the output conditions such as the S and R functions in the SR-FF which have been discussed previously.

Figure 11    JK- Flip-Flop with Clock type of rising transition

Table 5 Truth Table of JK-FF with Clock

 

Figure 12 Illustration of the workings JK-FF rising transition

The timing diagram in Figure 7.12 is an illustration of how this flip-flop works with the following analysis.

  1. In the initial state, all inputs are 0, and the output is Q=1
  2. At the time of rising transition of the first clock pulse (point a), where J=0, K=1, then this condition causes a reset state so that Q=0.
  3. At the time of transition up the second clock pulse (point c), where J=K=1(toggle), this condition changes the state of Q to 1.
  4. At the time of transition the third clock pulse rises (point e), where J=K =0, this condition does not change the state of Q so that it remains 1.
  5. At the time of the fourth clock pulse up transition (point g), where J = 1 while K = 0, this condition results in Q = 1.
  6. During the transition, the fifth clock pulse (point i) rises, where J=K=1 (toggle) so that Q changes against the original condition (changes to 0).
  7. During the transition, the sixth clock pulse rises (k point), where J=K=1 (toggle) so that Q changes against the original condition (changes to 1).

From the description above, it should be noted that the down transition of the clock pulse has no effect on the output of the flip-flop.

Figure 13 is given a type of down transition, which is indicated by the presence of a small circle on the clock terminal. The truth table is given in Table 6.


Figure 13  JK-FF with Clock transition down

Table 6   Truth Table JK-FF transition down

D-Flip-Flop with Clock

D -flip-flops are often also called data flip-flops with simpler operations. It has one input besides the clock and two outputs. This flip-flop is very useful for storing information in the form of binary data 0 or 1. The way it works is to move data from the D input terminal to the Q output when a clock transition occurs. There are two types, namely D-FF ascending transition and D-FF descending transition. The correct table for the ascending transition type is given in Table 7, and the symbols are given in Figure 14.

 

Table 7   Truth Table D-FF with Clock

 

Figure 14   D-FF rising transition Symbol

Figure 15  Illustration of working the D-FF rising transition

Diagram of time in Figure 15 is an illustration of how the flip-flop It works with the following analysis.

  1. At the initial state of output Q=1
  2. At the time of transition the first clock pulse increases (point a), where D=0, then Q changes to 0.
  3. At the time of transition the second clock pulse increases (point b), where D =1, then Q changes to 1.
  4. At the time of transition the third clock pulse increases (point c), where D=0, then Q changes to 0.
  5. At the time of transition the fourth clock pulse increases (point d), where D =1, then Q changes to 1.
  6. At the time of transition up the fifth clock pulse (point e), where D=1, then Q changes to 1.
  7. At the time of transition up the sixth clock pulse (point f), where D=0, then Q changes to 0.

From the above description, that data 1 or 0 will be sent to the output when there is an up transition of the clock pulse.

D-Flip-Flop Latch

This flip-flop is basically the same as a regular D-flip-flop, the difference is that the clock signal is replaced by a control input (Enable-E ). The way it works is described in Figure 7.17 and the symbol is given in Figure 16, and the correct table is given in Table 8.

Figure 16    D Latch Symbol

Table 7.8 Truth table D Latch

 

 

Figure 17   Illustration of how working the D Latch works

The timing diagram in Figure 17 is an illustration of how this flip-flop works with the following analysis: follows.

  1. In the initial condition Q = 0
  2. On condition until T1, output remains because EN = 0 (latch Q = 0) 3. At point T1-T2, where EN = 1, D = 1, Q = D
  3. At points T2-T3, where EN=0, then Q remains 1.(latch Q=1) 5. At points T3-T4, where EN=1, then Q=D.
  4. At point T4 and above, where EN=0, then Q=D last.(latch Q=0)

JK-FF with Synchronous Input

 

Figure 18    JK symbol with synchronous input

Table 9 Truth table D Latch

Figure 9  Illustration of how working JK Input Synchronous

The timing diagram in Figure 19 is an illustration of how this flip-flop works with the following analysis:

Point Operating
a Synchronous toggle on NGT clock
b Asynchronous SET=0
c Toggle synchronous
d Synchronous
e ToggleAsynchronous CLR=0
f Q remains 0 because CLR is still 0
g Synchronous toggle
  1. In the initial condition Q=0
  2. At condition up to T1, the output remains because EN=0 (latch Q=0) 3. At point T1-T2, where EN=1, D=1, then Q=D
  3. At point T2-T3, where EN=0, then Q remains 1.(latch Q=1)
    5. At point T3-T4, where EN=1, then Q=D.
  4. At the point T4 and above, where EN=0, the last Q=D.(latch Q=0)

 

Flip-Flop  Characteristics

The characteristics given here apply to all flip-flops. Usually given on the data sheet of an IC.

Propagation Delay Time

The time interval required After being given an input signal and producing an output

Set-Up Time

The minimum time required for the logic level to maintain input continuity of a flip-flop.

Maximum Clock Frequency

The maximum frequency that can be assigned to the flip-flop.

Power Dissipation

The amount of power consumption required flip-flop.

Pulse Width

The minimum pulse width given by the factory associated with the Clock, S and R inputs

Applications of Flip-flop

The Frequency Divider

Often in an application a frequency divider is needed to meet the needs of a digital system design. Figure 20 is a frequency divider circuit built from a JK-flip-flop that is assembled in a toggle state. The output of Q1 is the Seng of the input clock frequency, and Q2 is the Seng of Q1. Function FF1 is divisor 2, while FF2 is divisor 4. If you add more, the same function will occur, i.e. the Ready output of the flip-flop is always half of its clock input.

Figure 20    3-bit data transfer system

Parallel Data Storage

In digital systems, data is usually stored in the form of an array of bits representing a value, code, or other information. The data is stored in a series of flip-flops arranged in parallel. This condition is shown in Figure 21. Three D-FFs form 3 parallel data bits.

Three parallel data bits are assigned to the D-FF data terminal and all clock inputs are wired together. Data on the data terminal will be sent to the output terminal synchronously when there is a logic 0 to logic 1 change of the clock signal. This circuit is better known as the data transfer register. This will be discussed further

Figure 21   3-bit data transfer system

The data contained in D2..D0 will move simultaneously to Q2..Q0 when a positive transition occurs on theclock terminal

Counter

One popular application of flip-flops is the digital counter. The number of counter counts is 2 to the power of n, where n is the number of bits. For counter 2 bits will count 2 to the power of 2 = 4 counts (00, 01,10 and 11).

Figure 22  shows these conditions in a time diagram.

Figure 22    2-bits counter timing diagram

In the initial state, the output Q0 and Q1 logic 0. In the negative transition the clcok pulse 1 causes Q0 changes from 0 to 1 (toggle) because J and K are logic 1. Transition down Q0 causing Q1 changes from 0 to 1 because J and K are also toggled (J=K=1). On the down transition of clock pulse 3, returns Q0  changes from logic 0 to 1 (Togle), and will return toglr when clock 4 is on the turn transition. At the time of transition down Q0 Q1 changes from 0 to 1 (toggle) and when there is a down transition, Q0 will return to toggle. This is how it goes, and the complete condition is given in Table 10

Q1 Q0 Clock to
0 0 0
0 1 1
1 0 2
1 1 3

Table 10   Truth table of  2-bits counter timing diagram

Register

One of the most popular applications of flip-flops, is as memory. while in the computer system, namely registers. In computer systems it is known as RAM (Random access memory). These registers can store binary data temporarily, meaning that as long as there is a power supply the data is still stored and will be lost after the power supply is turned off.

Conclusion

  1. Flip-flop is a component that can store binary data 1 or 0
  2. In a computer system flip-flop is RAM type memory (can be erased and written)
  3. There are several types of flip-flops with functions and different applications